DSP - V06, Issue I

A Novel Reconfigurable Processor for Multi way Circuit partitioning Using Genetic Algorithm
Rajaram Sivasubramanian (1), Dhinesh Joseph (2) and Abhaikumar Varadhan (3)
Department of Electronics and Communication Engineering,
Thiagarajar college of Engineering, Anna University,
Madurai-625015, Tamilnadu (State), India
http://www.tce.edu

Abstract

Genetic Algorithms (GAs) are robust techniques based on natural selection that can be used to solve a wide range of problems including VLSI layout optimization, Circuit partitioning and Boolean satisfiability. This paper proposes ‘CIRPART’ – a novel architecture for implementing Genetic Algorithm (GA) used for circuit Multiway Partitioning in VLSI physical design automation. CIRPART is built upon ‘user programmable’, Field Programmable Gate Array (FPGA) device and employs a combination of Pipelining and Parallelization. CIRPART provides flexibility and also achieves speedups over software based GA. The design uses four modules and three external memories. The proposed design was coded in VHDL and was functionally verified by writing a test bench and simulating it using ModelSim. The design was synthesized on Xilinx Virtex V100CS144 FPGA chip using VHDL. CIRPART achieves more than 100% improvement in processing speed as compared to the software implementation while the quality of results remains unaltered.

Keywords: Genetic algorithm, Field Programmable Gate array, Multi-way circuit partitioning, VHDL

Rajaram Sivasubramanian, received his BE and ME degrees in Electronics and Communication Engineering from Thiagarajar College of Engineering and Alagappa Chettiar College of Engineering and Technology in 1994 and 1996, respectively, and pursuing PhD from Madurai Kamaraj University, Madurai, ,India. Currently, he is an Assistant Professor of Electronics and Communication Engineering at Thiagarajar College of Engineering, Madurai, India.He is a Member of IEEE, VLSI Society of India and published more than 25 papers in both International and National Conferences. His Research interests include FPGA Design, VLSI  testing, Design Optimization.

Abhaikumar Varadhan, received his BE and M.E. degree from PSG college of Technology, Coimbatore, India in 1977 and 1979 respectively. He received his PhD degree from Indian Institute of Technology, Madras, India in 1987. Currently, he is the Principal and Head of Electronics and Communication Engineering at Thiagarajar College of Engineering, Madurai ,India. He is a senior Member of IEEE. He is the recipient of two awards for research, teaching and advising excellence.He has co-authored 70 technical papers in reputed journals, International and National Conferences.

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