An Efficient
Implementation of IS-95A CDMA Transceivers through FPGA
Rajaram Sivasubramanian1and
Abhaikumar Varadhan2
Department of Electronics and Communication Engineering,
Thiagarajar college of Engineering,
Anna University,
Madurai-625015,Tamilnadu(State),India
Abstract
In this paper, proficient
architectures for IS-95A CDMA Transceivers are modeled and
optimized for hardware implementation on FPGA. The
efficiency of the transceivers is improved by incorporating
a novel Interleaver, developed for mobile communication
channel. The Interleaver improves the performance of the
transceivers at lower SNR levels. The architecture applies a
new-fangled scheme for implementing Viterbi decoder and
thereby results in reduced computation operations and memory
requirements. The model is implemented in Xilinx V100CS144
chip using VHDL. The FPGA hardware uses 88% of a 1200 slice
VIRTEX FPGA device and delivers a satisfactory performance
with a reduction in memory by 7.6% (for rate 1/2),40.9% (for
rate 1/3) and with maximum net delays much within the
allowable limits of maximum data rate of 9.6Kbps.
Keywords:
IS-95
A CDMA, Interleaver, Viterbi Decoder, Field Programmable
Gate array(FPGA) , VHDL
 |
Rajaram
Sivasubramanian, received his BE and ME
degrees in Electronics and Communication Engineering
from
Thiagarajar College of Engineering and Alagappa
Chettiar College of Engineering and Technology in
1994 and 1996, respectively, and pursuing PhD from
Madurai Kamaraj University, Madurai, ,India.
Currently, he is an Assistant Professor of
Electronics and Communication Engineering at
Thiagarajar College of Engineering, Madurai, India..
He is a Member of IEEE,VLSI Society of India and
published more than 25 papers in both International
and National Conferences. His Research interests
include FPGA Design, VLSI testing, Design
Optimization. |
 |
Abhaikumar Varadhan, received his BE and
M.E. degrees in Electronics and Communication
Engineering from PSG college of Technology,
Coimbatore,India in 1977 and 1979 respectively. He
received his PhD degree from Indian Institute of
Technology, Madras, India in 1984. Currently, he is
the Principal and Head of Electronics and
Communication Engineering at Thiagarajar College of
Engineering, Madurai ,India. He is a senior Member
of IEEE. He is the recipient of two awards for
research, teaching and advising excellence. He has
co-authored 70 technical papers in reputed journals,
International and National Conferences. |
BibTex:
AUTHOR = {
Rajaram
Sivasubramanian and Abhaikumar Varadhan},
TITLE = {
An Efficient
Implementation of IS-95A CDMA Transceivers
through FPGA
},
JOURNAL = {ICGST
The International Journal on Digital Signal
Processing,
DSP},
YEAR = {2006},
VOLUME = {06},
ISSUE = {I},
PAGES = {23--30}
}
( Full
paper, 760KB )
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