A Novel Approach to Test Data Compression for BIST and its Implementation
Rajaram Sivasubramanian¹ Karthick Ramkumar² and Abhaikumar Varadhan³
Department of Electronics and Communication Engineering, Thiagarajar college of Engineering, Anna University, Madurai-625015,Tamilnadu(State),India

Abstract

In this paper, a newly fangled test data compression technique for the deterministic Built-In-Self Test (BIST ) is proposed. The main focus of this paper is to reduce memory storage requirement of the test vectors without any modification in the test application time. Here, the test vectors are first encoded and then compressed. The required test patterns are regenerated from the compressed data stored in the memory using the proposed novel decoder and customized counter circuit. Test vector generation had been simulated, including Minimal set test vectors identification, encoding of test vectors and compression using the algorithm, developed in C Language. The hardware portion of the Testing equipment is implemented in FPGA hardware using VHDL and functionally verified. The proposed scheme requires less memory to store test data while aids very high fault coverage.

Keywords: Data Compression, VHDL, Built-In-Self-Test (BIST), FPGA, Design for Testability(DFT)

(Full paper, 590KB )

	Rajaram Sivasubramanian, received his BE and ME degrees in Electronics and Communication Engineering from Thiagarajar College of Engineering and Alagappa Chettiar College of Engineering and Technology in 1994 and 1996, respectively, and pursuing PhD from Madurai Kamaraj University, Madurai, ,India. Currently, he is an Assistant Professor of Electronics and Communication Engineering at Thiagarajar College of Engineering, Madurai, India.He is a Member of IEEE, VLSI Society of India and published more than 25 papers in both International and National Conferences. His Research interests include FPGA Design, VLSI  testing, Design Optimization.
	Karthick Ramkumar, Received his B.E degree from Thiagarajar College of  Engineering,Madurai in the year 2003.His research interest includes VLSI Design and Testing ,FPGA Implementation and Genetic Algorithms. Now He is with Cognizant Technology Solutions (P) Ltd, Chennai as a senior Software Engineer.
	Abhaikumar Varadhan, received his BE and M.E. degree from PSG college of Technology, Coimbatore, India in 1977 and 1979 respectively. He received his PhD degree from Indian Institute of Technology, Madras, India in 1987. Currently, he is the Principal and Head of Electronics and Communication Engineering at Thiagarajar College of Engineering, Madurai ,India. He is a senior Member of IEEE. He is the recipient of two awards for research, teaching and advising excellence.He has co-authored 70 technical papers in reputed journals, International and National Conferences.

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