ICGST- DSP Journal

GATE AND SUBTHRESHOLD LEAKAGE REDUCED SRAM CELLS
H.Mangalam* and K.Gunavathi**
* Department of Electronics and Communication Engineering Sri Krishna College of Engineering and Technology Coimbatore – 641008 Tamilnadu, India
** Department of Electronics and Communication Engineering PSG College of Technology Coimbatore –641004 Tamilnadu, India

Abstract

High leakage currents in deep submicron regimes are becoming a major contributor to total power dissipation of CMOS circuits as the threshold voltage, channel length and gate oxide thickness are scaled. Consequently, identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low power applications. This provides the motivation to explore the design of low leakage SRAM cells. In this paper, a novel asymmetric SRAM cell (SA) with an extra transistor compared to conventional 6T SRAM cell is proposed that reduces the gate leakage. To reduce the sub-threshold leakage further, an adaptive voltage level (AVL) circuit is added to this cell, which controls the effective voltage across the SRAM cell in inactive mode. Two schemes are employed; one in which the supply voltage is reduced and the other in which the ground potential is increased. SPICE Simulations are performed with 130nm CMOS technology process file and the leakage currents of all the cells are measured and compared. Simulation results revealed that there is a significant reduction in leakage current for this proposed cell with the AVL circuit reducing the supply voltage.

(Full paper, 361KB )

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