Abstract

The objective of the paper is to implement an ADALINE algorithm, for computation of Total Harmonic Distortion (THD) of harmonics in load current waveform on a Field Programmable Gate Array (FPGA). More power electronic converters (like SMPS, UPS, etc.) are added in the electrical distribution, due to their higher efficiency. But these converters, which are nonlinear loads, generate harmonics. Harmonics cause many ill effects in the power system and reduce Power Quality. Measurement of harmonics and computation of THD are important to assess the Power Quality.  Harmonics have been measured by Fast Fourier Transform (FFT) executed on a microprocessor or a Digital Signal Processor.    The FFT algorithm requires a minimum of 1000 samples from 10 cycles for a supply frequency of 50Hz. Neural Network algorithms are proving their efficacy in many complex situations. FPGAs are particularly suitable for implementing NN algorithms due to their hardware parallelism. This paper presents the results of implementation of ADALINE on an FPGA for computation of THD. The proposed implementation requires only 100 samples from 1 cycle of the load current. The results obtained using the proposed method are compared with that of the conventional FFT results and found to be very close.

 Keywords:  Harmonics, ADALINE, FPGA implementation.

(P1110830268, 728 KB)

TITLE = {Implementation of ADALINE Algorithm on a FPGA for Computation of Total Harmonic Distortion of load current},

JOURNAL = {ICGST International Journal on Automatic Control and Systems Engineering, ACSE},