VLSI
Floor Planning relying on Differential Evolution Algorithm
1D.Jackuline
Moni,2 S. Arumugam and 3D.Gracia
Nirmala Rani
1, 3 ECE Department,
Karunya University,
Coimbatore, India.
2. Chief Executive,
Bannariamman
Educational Trust, Coimbatore
Abstract:
This paper presents a novel approach to solve the VLSI (Very
Large Scale Integration) floor planning problems. This
approach is based on Differential Evolution (DE) which
optimizes both chip area and total wire length without
overlaps in VLSI macro cell placement. Differential
Evolution algorithm requires few control parameters, and has
fast convergence. B*tree representation is used because it
is very fast, flexible and easy for implementation. DE has
been implemented and tested on popular benchmark problems.
Experimental results show that DE can quickly produce
optimal solutions for all tested benchmark problems.
Keywords: Floorplanning, Differential
Evolution, B*tree Representation
( Full Paper,
511 KB)

Biographies:
 |
D.Jackuline
Moni did B.Tech in Electronics Engineering at Anna
University and M.E in Applied Electronics at
Bharathiar University in 1987 &1996 respectively.
She is working as an Associate Professor in ECE
Department, Karunya University, Coimbatore, South
India. Her research area includes CAD VLSI, Low
Power &High Speed VLSI Design, Microprocessors &
Microcontrollers. She has published more than ten
research papers in International and National
journals and conferences
|
 |
Dr. S. Arumugam, received the PhD. Degree in
Computer Science and Engineering from Anna
University, Chennai in 1990.He also obtained his
B.E(Electrical and Electronics Engg.) and M.Sc. (Engg)
(Applied Electronics)Degrees from P.S.G College of
Technology, Coimbatore, University of Madras in 1971
and 1973 respectively. He worked in the Directorate
of Technical Education, Government of Tamil Nadu
from 1974 at various positions from Associate
Lecturer, Lecturer, Assistant Professor, Professor,
Principal, Additional Director of Technical
Education. He has guided 4 PhD scholars and guiding
10 PhD scholars. He has published 70 technical
papers in International and National journals and
conferences. His area of interest includes network
security, Biometrics and neural networks. Presently
he is working as Chief Executive, Bannariamman
Educational Trust, Coimbatore. |
 |
D.
Gracia Nirmala Rani, received her B.E(ECE) Degree
from Syed Ammal Engineering College, Madurai Kamaraj
University, South India and M.E(VLSI Design) from
karunya University, Coimbatore in 2005 and 2007
respectively. Presently she is working as a Lecturer
in ECE Department, Karunya University Coimbatore,
India. Her area of interest includes CAD VLSI, ASIC
Design
|

BibTex:
@ARTICLE{P1120708002,
AUTHOR = {D.Jackuline
Moni and S. Arumugam and D.Gracia Nirmala Rani},
TITLE ={VLSI
Floor Planning relying on Differential Evolution Algorithm},
JOURNAL = {ICGST
International Journal on Artificial Intelligence and Machine
Learning, AIML},
YEAR = {2007},
VOLUME = {7},
ISSUE ={1},
PAGES={62--67}
}
( Full Paper,
511 KB)
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