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Performance Evaluation of VHDL Implementation of Proposed SAFER+ Security Algorithm and Pipelined AES Security Algorithm for Bluetooth Security Systems *(Research Scholar) Asso .Prof., Department of ECE, Bannari Amman Institute of Technology, Sathyamangalam, ** Asst. Prof, Department of EEE, PSG College of Technology, Coimbatore
Abstract
In this paper, a
comparison of Novel architectures of VHDL Implementation
of the SAFER+ encryption algorithm and Pipelined AES
algorithm are presented. Performance of the above
security algorithms are evaluated based on the
parameters – Data Throughput, and Frequency. The whole
design was captured entirely in VHDL language using a
bottom-up design and verification methodology. The
proposed SAFER+ algorithm achieves a data throughput of
1096.035 Mbits/sec at a clock frequency of 77.065 MHz.
The Pipelined architecture of AES algorithm achieves a
data throughput of 359.82 MB/s, at a clock frequency of
50.6 MHz. On comparison, proposed SAFER+ algorithm
proves to be better for implementation in Bluetooth
devices than the pipelined AES algorithm.
Keywords
Security And Fast Encryption Routine, Encryption,
Authentication, stream cipher, Pseudo Hadamard
Transformation, Advanced Encryption Standard, Sub bytes,
Shift rows, Mix columns, Add round key.
(
BibTex: @ARTICLE{P1140906639,
AUTHOR = {D. Sharmila and R. Neelaveni},
TITLE = {Performance Evaluation of VHDL Implementation of Proposed SAFER+ Security Algorithm and Pipelined AES Security Algorithm for Bluetooth Security Systems }, JOURNAL = {ICGST International Journal on Computer Network and Internet Research, CNIR}, YEAR = {2009}, VOLUME = {09}, ISSUE = {I},
PAGES= {11--18}
}
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