Autonomously Restructured Fault Tolerant Image Enhancement Filter
*A.Guruva Reddy, **K.Sri Rama Krishna, ***M.N.Giri Prasad and @ K.Chandra Bhushana Rao
*Research Scholar, Electronics and Communication Department, JNT University, Hyderabad, India
** Professor and Head, Dept. of ECE, V R Siddartha Engg College, Vijayawada.
***Professor and Head, Dept. of ECE, JNT University, Pulivendala
@ Principal, V.S. Lakshmi Engineering College for Women, Kakinada,

 Abstract:

 Reconfigurable hardware based image enhancement technique when compared to the conventional method has an improved image quality even under adverse conditions such as contrast reversal and intensity gradients, angular uncertainties, blur caused by changes in depth field, scale changes, partial obliteration or missing features. In addition, parallel architectures can be used to ease the enormous computational load due to different operations conducted on image data sets. Reconfigurable computing is a new concept in the development of online adaptive machines. But, on the pessimistic side as the evolved circuit becomes large, the testability of the circuit becomes important and inherently testable logic need to coexist for autonomous restructuring in case of any internal fault. In this paper, in the first phase, schemes for testing the configured processing elements of a reconfigurable circuit evolved for image enhancement application is presented. In the second phase, the internal elements of the evolved circuit, if found faulty, is restructured such that the sparse Processing Elements (PE’s) replace the faulty PE’s both functionally and structurally. Simulation results show that the evolved circuit is inherently testable and can restructure itself by avoiding the faulty PE’s and make
use of sparse ones.

Keywords: Image Enhancement Filter, Reconfigurable computing, Embedded cores, Autonomous Restructuring, fault tolerant circuit.

(P1150830001, 552 KB)