| Paper Details: | Downloads: 517 |
| Serial Number: | P1140906639
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| Title: | Performance Evaluation of VHDL Implementation of Novel Architecture of SAFER+ and Pipelined AES Security Algorithms for Bluetooth Security Systems
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| Authors: | D.Sharmila and R.Neelaveni
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| Abstract: | In this paper, a comparison of Novel architectures of VLSI Synthesis of the SAFER+ encryption algorithm and Pipelined AES algorithm are presented. Performance of the above security algorithms are evaluated based on the parameters – Data Throughput, and Frequency. The whole design was captured entirely in VHDL language using a bottom-up design and verification methodology. The proposed Novel architecture of VLSI synthesis of the SAFER+ algorithm achieves a data throughput of 1096.035 Mbits/sec at a clock frequency of 77.065 MHz. The Pipelined architecture of AES algorithm achieves a data throughput of 359.82 MB/s, at a clock frequency of 50.6 MHz. On comparison, proposed SAFER+ algorithm proves to be better for implementation in Bluetooth devices than the AES algorithm.
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| Keywords: | Security And Fast Encryption Routine, stream cipher, Psuedo Hadamard Transformation, Advanced Encryption Standard, Sub bytes, Shift rows, Mix columns, Add round key.
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| Journal/Conference: | International Journal of Computer Networks and Internet Research
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| Volume: | 9
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| Issue: | 1
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| Submission Date: | 2/6/2009 12:00:00 AM
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| Review Date: | 2/17/2009 12:00:00 AM
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| Publishing Date: | 3/19/2009 12:00:00 AM
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| Article Downloads: | 517
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