Paper Details: Downloads: 535
Serial Number: P1170850529
Title: Design and Analysis of Dynamically Configurable Bus Arbiters for SoCs
Authors: S.Hema Chitra and B. Dr. P.T.Vanathi
Abstract: In System on Chip (SoC) buses, intellectual properties (IPs) need to communicate with each other to access the required functionality. When the SoC bus is connected with more IPs, contentions occur while multiple IPs requests the bus at the same time. This makes on-chip bus based communication a major challenge for the system designer in the current SoC technology. In this paper, new dynamically configurable bus arbiters are proposed to handle the discrepancy of the existing arbitration algorithms. This paper also examines the effect of arbitration policies in different on-chip buses which help the designers to compare the various standard bus architectures. The various parameters considered for performance evaluation are dynamic power, area and latency.
Keywords: SoC, On-chip bus, dynamically configurable arbiter, latency.
Journal/Conference: International Journal of Programmable Devices, Circuits, and Systems
Volume: 8
Issue: 1
Submission Date:
Review Date: 1/11/2009 12:00:00 AM
Publishing Date: 1/25/2009 12:00:00 AM
Article Downloads: 535
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