| Paper Details: | Downloads: 769 |
| Serial Number: | P1170950105
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| Title: | Design and Implementation of a Real Time FPGA Based CFAR Processor for Radar Target Detection Using ML403 FPGA Development Board
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| Authors: | Boualem Magaz and Toufik Mabed and Ali Abbadi and M’hamed Hamadouche and Adel Belouchrani
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| Abstract: | The improvement in the development of theoretical aspect of CFAR radar detection is advanced and very promising, yet the practical hardware aspect is still beyond the required high computational signal processing operations. In this paper, a configurable Field Programmable Gate Array (FPGA) based hardware architecture for Ordered Statistics (OS)-CFAR processor for radar target detection is presented. The proposed architecture is based on an efficient procedure for FPGA implementation of the OS-CFAR detector, based on the (N-K+1)-th maximum determination. By showing that the determination of the K-th order out of N reference cells is equivalent to selecting the (N + 1 - K)-th maximum, the detector that uses N reference cells can be implemented using only (N- 1) comparators and (N-1) inverters. The proposed structure, adapted to the ASR-9 radar parameters, is designed, implemented, and evaluated on the ML403 FPGA board. The proposed architecture shows that it can be implemented with the advantages of a parallel structure and allows an important optimization of the required FPGA hardware resources utilization. The system has the advantages of being simple, fast, and flexible with low development cost. For a reference window of 16 range cells, the experimental results carried out using Xilinx development kit showed that the proposed architecture works properly with a processing speed of 50MHz (up to 122 MHz using external clock). The execution time to perform the overall OS-CFAR detection algorithm is 0.819ms for a data set of 1000 range cells. The FPGA implementation results are presented and discussed
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| Keywords: | FPGA, Implementation, OS-CFAR processor, Radar
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| Journal/Conference: | International Journal of Programmable Devices, Circuits, and Systems
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| Volume: | 9
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| Issue: | 1
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| Submission Date: | 9/1/2009 12:00:00 AM
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| Review Date: | 10/1/2009 12:00:00 AM
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| Publishing Date: | 12/1/2009 12:00:00 AM
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| Article Downloads: | 769
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