Paper Details: Downloads: 610
Serial Number: P1180625003
Title: A Novel Approach to Test Data Compression for BIST and its Implementation
Authors: Rajaram Sivasubramanian and Karthick Ramkumar and Abhaikumar Varadhan
Abstract: In this paper, a newly fangled test data compression technique for the deterministic Built-In-Self Test (BIST ) is proposed. The main focus of this paper is to reduce memory storage requirement of the test vectors without any modification in the test application time. Here, the test vectors are first encoded and then compressed. The required test patterns are regenerated from the compressed data stored in the memory using the proposed novel decoder and customized counter circuit. Test vector generation had been simulated, including Minimal set test vectors identification, encoding of test vectors and compression using the algorithm, developed in C Language. The hardware portion of the Testing equipment is implemented in FPGA hardware using VHDL and functionally verified. The proposed scheme requires less memory to store test data while aids very high fault coverage.
Keywords: Data Compression, VHDL, Built-In-Self-Test (BIST), FPGA, Design for Testability(DFT)
Journal/Conference: International Journal of Digital Signal Processing
Volume: 6
Issue: 1
Submission Date: 7/1/2006 12:00:00 AM
Review Date: 8/1/2006 12:00:00 AM
Publishing Date: 9/1/2006 12:00:00 AM
Article Downloads: 610
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