Paper Details: Downloads: 515
Serial Number: P1180630001
Title: An Efficient Implementation of IS-95A CDMA Transceivers through FPGA
Authors: Rajaram Sivasubramanian and Abhaikumar Varadhan
Abstract: In this paper, proficient architectures for IS-95A CDMA Transceivers are modeled and optimized for hardware implementation on FPGA. The efficiency of the transceivers is improved by incorporating a novel Interleaver, developed for mobile communication channel. The Interleaver improves the performance of the transceivers at lower SNR levels. The architecture applies a new-fangled scheme for implementing Viterbi decoder and thereby results in reduced computation operations and memory requirements. The model is implemented in Xilinx V100CS144 chip using VHDL. The FPGA hardware uses 88% of a 1200 slice VIRTEX FPGA device and delivers a satisfactory performance with a reduction in memory by 7.6% (for rate 1/2),40.9% (for rate 1/3) and with maximum net delays much within the allowable limits of maximum data rate of 9.6Kbps.
Keywords: IS-95 A CDMA, Interleaver, Viterbi Decoder, Field Programmable Gate array(FPGA) , VHDL
Journal/Conference: International Journal of Digital Signal Processing
Volume: 6
Issue: 1
Submission Date: 7/1/2006 12:00:00 AM
Review Date: 8/1/2006 12:00:00 AM
Publishing Date: 9/1/2006 12:00:00 AM
Article Downloads: 515
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