| Abstract: | This paper presents the method to reduce dynamic switching power consumption of digital system using Data Transition Power Diminution technique (DPDT). This Technique is used on modified booth multipliers, adders and FIR Filters for reducing power. When most significant bits of one of the operands of multiplication are zero, then the corresponding circuit may be turned off, because they do not involve in the computation of results. Eliminating the data transition power, not only save the power consumed in the adder and multiplier but also decrease the power consumption due to glitching, which will affect the next stages of the circuit. DPDT reduces delay, computation time and dynamic power dissipation. DPDT equipped adder and multiplier are used to design a FIR filter. The proposed FIR Filter was implemented using Xilinx Spartan 3E(3s200ft256-4)FPGA and the performance of the adder, signed Array multiplier, Booth multiplier, FIR filter using signed Array multiplier, FIR filter using Booth multiplier without DPDT, with dynamic-range determination (DRD)unit and with DPDT were analyzed and the result shows that proposed technique reduces the power consumption, area and delay by 31.4%, 18% and 2.4 % respectively than the existing Technique with dynamic range determination unit (DRD).
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