| Paper Details: | Downloads: 520 |
| Serial Number: | P1180848514
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| Title: | Power Delay Optimized Adder for Multiply and Accumulate Units
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| Authors: | P.Ramanathan and P.T.Vanathi
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| Abstract: | The prevalent blocks used in digital signal processing hardware are the adder, multiplier and delay elements. Better the performance of adder structure better will be the performance of multipliers in total aspect. Reducing power dissipation, delay and area at the circuit level is considered as one of the major factors in developing low power systems. In this paper we have introduced a new 14 transistor (14 T) full adder which has better power, delay performance than the existing adders. Performance comparison of the proposed 14 T adder has been made by comparing its performance with 10T SERF, 10T CLRCL, the existing 14T full adders. The proposed 14 T full adder structure has improved performance characteristics and suitable for Array, Carry Save and Dadda multipliers. Also three versions of 3 tap FIR filter namely Broadcast, Unfolded Broadcast, Unfolded and Retimed Broadcast structures have been implemented using three different multipliers. Each of these multipliers used for the Filters are implemented using all the existing full adders and the proposed 14 T full adder. Results show that circuits implemented using proposed 14T full adder have better power, delay and cascaded performance when compared with the peer ones. All the simulations were carried out using TSMC Complementary Metal Oxide Semiconductor (CMOS) 180 nm technology file with a supply voltage of 1.8V. Tools used are Cosmos and Path mill of Synopsys.
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| Keywords: | Array Multiplier, Carry Save multiplier, Dadda Multiplier, FIR Filter, Unfolding and Retiming.
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| Journal/Conference: | International Journal of Digital Signal Processing
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| Volume: | 9
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| Issue: | 1
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| Submission Date: | 11/24/2008 12:00:00 AM
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| Review Date: | 2/10/2009 12:00:00 AM
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| Publishing Date: | 2/22/2009 12:00:00 AM
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| Article Downloads: | 520
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