Implementation of 128/256 Bit Data Bus Microprocessor Core on FPGA

Weng Fook Lee *, Ali Yeon Md. Shakaff **

(*) Emerald Systems Design Center , (**) Universiti Malaysia Perlis
(*) http://www.emersysdesign.com, (**) http://www.unimap.edu.my

Abstract:

This paper shows the implementation of a large data bus size microprocessor core of 128/256 bits on an Altera Stratix 2 FPGA using a superscalar architecture of 3 parallel pipes with 4 stage pipeline as shown in Figure 1. The system level implementation utilizing the implemented microprocessor core on FPGA is shown in Figure 2. The micro-architecture of the microprocessor core architecture of Figure 1 is implemented using four pipe stages of fetch, decode, execute and writeback with a shared register file for all 3 parallel pipes, as shown in Figure 3.

Keywords: Large data bus size microprocessor, VLIW, FPGA

Biography:

Weng Fook Lee is a Senior MTS at Emerald Systems Design Center specialising in RTL coding, ASIC synthesis and FPGA implementation. He is also the inventor and co-inventor of 14 design patents granted by the US Patent and Trademark Office, author of two IC design books titled “VHDL Coding and Logic Synthesis With Synopsys”, Academic Press Publication, ISBN 0124406513 and “Verilog Coding For Logic Synthesis”, Wiley Publication, ISBN 0471429767.

Ali Yeon Md. Shakaff is currently a Professor and also the Deputy Vice-Chancellor (Academic and International Affairs) at Universiti Malaysia Perlis (UniMAP). He obtained his Ph.D. in Electronic Engineering from the University of Newcastle-upon-Tyne, England in 1987. His current research interests are in Embedded Systems Design and Biomimetic Sensors.

BibTex

@ARTICLE{PDCS0712001,

AUTHOR = {Weng Fook Lee and Ali Yeon},

TITLE = {Implementation of 128/256 Bit Data Bus Microprocessor Core on FPGA},

}

(PDCS0712001,  655 KB)