High Reliable Self Repairable Architecture for SRAM

 N.M.Sivamangai  and K.Gunavathi

Department of Electronics and Communication Engineering, PSG College of Technology, Coimbatore, Tamilnadu, India

Abstract:

In scaled technologies, the increasing process parameter variations results in various failures in CMOS circuits. The reliability of static random access memory (SRAM) with its single cell designed with six-transistor CMOS technology is greatly affected due to the parameter variations (in particular, threshold voltage (Vt)). The adaptive repairing technique, such as adaptive body bias applied to SRAM improves the reliability. However, in spite of applying the adaptive body bias to high Vt corner there is only a lesser reduction in the deviation of Vt from the nominal value resulting in improper repairing scheme. Hence as an attempt to increase the yield of SRAM, a high reliable self repairable SRAM architecture has been proposed in this paper based on zone based adaptive body bias (ZBABB) technique. In this technique, the high Vt corner is partitioned into two different zones of zone I and zone II, by monitoring the leakage current of the SRAM array. When an optimum body bias is applied to the partitioned zones, there is an increase in the reduction of deviation of Vt from the nominal value, thus reducing the number of functional failures and accounting for a more reliable architecture. The proposed self repairable SRAM architecture improves the design yield by 40%-50%.

Keywords: scaled technologies, process parameter variations, Static Random Access Memory (SRAM), body bias.

(P1170909662 971 KB)

@ARTICLE{P1170909662,

AUTHOR = {N.M.Sivamangai  and K.Gunavathi},

TITLE = {High Reliable Self Repairable Architecture for SRAM},

}

(P1170909662 971 KB)