Editors: Prof. Dr. Mohamed-Salim BOUHLEL and Ashraf Aboshosha
| @ARTICLE |
{P1170909662, |
| AUTHOR = |
{N.M.Sivamangai and K.Gunavathi}, |
| TITLE = |
{High Reliable Self Repairable
Architecture for SRAM}, |
| JOURNAL = |
{ICGST International Journal on Programmable
Devices, Circuits and Systems, PDCS}, |
| YEAR = |
{2009}, |
| MONTH= |
{December}, |
| VOLUME = |
{09}, |
| ISSUE = |
{I}, |
| PAGES= |
{1--8}, |
| ABSTRACT= |
{In scaled technologies, the increasing process parameter variations results in various failures in CMOS circuits. The reliability of static random access memory (SRAM) with its single cell designed with six-transistor CMOS technology is greatly affected due to the parameter variations (in particular, threshold voltage (Vt)). The adaptive repairing technique, such as adaptive body bias applied to SRAM improves the reliability. However, in spite of applying the adaptive body bias to high Vt corner there is only a lesser reduction in the deviation of Vt from the nominal value resulting in improper repairing scheme. Hence as an attempt to increase the yield of SRAM, a high reliable self repairable SRAM architecture has been proposed in this paper based on zone based adaptive body bias (ZBABB) technique. In this technique, the high Vt corner is partitioned into two different zones of zone I and zone II, by monitoring the leakage current of the SRAM array. When an optimum body bias is applied to the partitioned zones, there is an increase in the reduction of deviation of Vt from the nominal value, thus reducing the number of functional failures and accounting for a more reliable architecture. The proposed self repairable SRAM architecture improves the design yield by 40%-50%}, |
| NOTE= |
{scaled technologies, process parameter variations, Static Random Access Memory (SRAM), body bias}
}
|
(Status: Accepted)
| @ARTICLE |
{P1170853554, |
| AUTHOR = |
{M.B. Abdelhalim and H. K. Aslan and A. Mahmoud and H. Farouk}, |
| TITLE = |
{A DESIGN FOR AN FPGA IMPLEMENTATION
OF RIJNDAEL CIPHER}, |
| JOURNAL = |
{ICGST International Journal on Programmable Devices, Circuits and Systems, PDCS}, |
| YEAR = |
{2009}, |
| MONTH= |
{December}, |
| VOLUME = |
{09}, |
| ISSUE = |
{I}, |
| PAGES= |
{9--15}, |
| ABSTRACT= |
{Our aim is to simulate the Rijndael cipher using Field Programmable Gate Array (FPGA) to achieve low cost, ease of implementation, availability “FPGAs can be bought off the shelf“, high flexibility including capability of frequent modifications of hardware, and low cost of the final product. We propose a modified implementation of Rijndael, the Advanced Encryption Standard (AES) based on the fact that any FPGA includes built in memory block where we store all the results of the fixed operations. The modification gives an 11% reduction in area and 25% increase in speed (throughput) compared with the original design. Our design gives the highest throughput and area utilization over all the Iterative Looping (IL) based FPGA implementations. In the original design, the decryption algorithm was not implemented. Our implementation of the decryption algorithm gives better results than the other IL based FPGA implementations}, |
| NOTE= |
{Rijndael cipher, FPGA, memory block, encryption, decryption}
}
|
(Status: Accepted)
| @ARTICLE |
{P1170912689, |
| AUTHOR = |
{Pankaj U. Lande and Sanjay N.
Talbar and G.N. Shinde}, |
| TITLE = |
{FPGA Implementation of Image
Adaptive Watermarking Using Human Visual Model}, |
| JOURNAL = |
{ICGST International Journal on Programmable Devices, Circuits and Systems, PDCS}, |
| YEAR = |
{2009}, |
| MONTH= |
{December}, |
| VOLUME = |
{09}, |
| ISSUE = |
{I}, |
| PAGES= |
{17--22}, |
| ABSTRACT= |
{In this paper we describe blind, robust and computational efficient algorithm in DHT (Discrete Hadamard Transform) domain. The algorithm was implemented on FPGA (Field Programmable Gate Array) and tested for various images. The algorithm was developed using the human visual system (HVS) based on DHT. This allows embedding the watermark with maximum gain factor within the imperceptible regions of the image. The objective is to develop the low power real time and reliable watermarking scheme. We have synthesized this prototype on Xilinx FPGA. The proposed scheme is scheme shows the less hardware utilization and robust against the attacks}, |
| NOTE= |
{HVS, PN, DHT, FPGA}
}
|
(Status: Accepted)
| @ARTICLE |
{P1170950101, |
| AUTHOR = |
{Rima Hamoui and Nacer Abouchi and Thierry Tixier and Gael Pillonnet and Yasmina Fellah}, |
| TITLE = |
{Computer Aided Microsystem Design:
An Automatic VHDL-AMS Generator of Sensor Model}, |
| JOURNAL = |
{ICGST International Journal on Programmable Devices, Circuits and Systems, PDCS}, |
| YEAR = |
{2009}, |
| MONTH= |
{December}, |
| VOLUME = |
{09}, |
| ISSUE = |
{I}, |
| PAGES= |
{23--28}, |
| ABSTRACT= |
{In this paper a development of a platform for facilitating
designs of microsystems is discussed, in particular, the
design of the interface between the sensor and its
associated electronics. Also reported is a technique for
automatically generating VHDL-AMS sensor models.
The objective is to enable a non-specialist, with only a
basic experience in sensor- interface design or modeling,
to model his or her own VHDL-AMS sensor, and
simulate it to its electronic environment. Indeed, only an
acquaintance with the physics of sensor/interface is all
that is assumed}, |
| NOTE= |
{sensors, automatic generation, microsystems,
modelling, VHDL-AMS}
}
|
(Status: Accepted)
| @ARTICLE |
{P1170950102, |
| AUTHOR = |
{Boualem Magaz and Ali Abbadi and Toufik Mabed and M’hamed Hamadouche and Adel Belouchrani}, |
| TITLE = |
{Using D.S.P in Radar Domain
Application : Optimal Implementation of CFAR Detection Algorithms on
TMS320C6711 DSP}, |
| JOURNAL = |
{ICGST International Journal on Programmable Devices, Circuits and Systems, PDCS}, |
| YEAR = |
{2009}, |
| MONTH= |
{December}, |
| VOLUME = |
{09}, |
| ISSUE = |
{I}, |
| PAGES= |
{29--34}, |
| ABSTRACT= |
{In this paper, we present an efficient implementation
method of Constant False Alarm Rate (CFAR) detectors
that use linear combination of the noise level to estimate
the threshold using the Texas Instruments
TMS320C6711 processor. We present also a parametric
expression for an optimal number of the reference
window size for threshold estimation. Morever, we
present the amelioration using the Generalized Automatic
Sliding Window technique (GASW) for the CA-CFAR
detector and it’s derivates, the GO-CFAR and the SOCFAR.
Implementation results are presented and
discussed}, |
| NOTE= |
{CFAR, DSP, Implementation, Radar,
TMS320C6711}
}
|
(Status: Accepted)
| @ARTICLE |
{P1170950103, |
| AUTHOR = |
{Ali ABBADI and Jugurtha OUKSILI and Toufik MABED1 and Boualem MAGAZ}, |
| TITLE = |
{Study and Implementation on FPGA Board of a Digital Beamformer Algorithm
for Uniform Circular Antenna Array}, |
| JOURNAL = |
{ICGST International Journal on Programmable Devices, Circuits and Systems, PDCS}, |
| YEAR = |
{2009}, |
| MONTH= |
{December}, |
| VOLUME = |
{09}, |
| ISSUE = |
{I}, |
| PAGES= |
{35--39}, |
| ABSTRACT= |
{The beamforming is a spatial filtering technique that uses
the output of a sensor array to preserve the amplitude of a
signal in a desired look direction relative to background
noise and directional interference. It’s the combination of
received signals from a set of each of the antenna
elements to form a directional antenna. The formed beam
can be pointed electronically, although the antenna does
not rotates physically.
In this work, we propose an FPGA implementation
approach of digital beamforming algorithm for Uniform
Circular antenna Array (UCA) using Virtex-II™
V2MB1000 Development Board. A description of the
antenna geometry and the beamformer algorithm is
presented. The architecture of the implementation
approach, the implementation constraints and the
implementation the results are discussed}, |
| NOTE= |
{Beamforming, FPGA implementation,
Antenna array, Uniform Circular Array}
}
|
(Status: Accepted)
| @ARTICLE |
{P1170950104, |
| AUTHOR = |
{M. Moussa and K. Belkadi}, |
| TITLE = |
{Modeling and Simulation of Flow in a Imaging Service of HMRUO}, |
| JOURNAL = |
{ICGST International Journal on Programmable Devices, Circuits and Systems, PDCS}, |
| YEAR = |
{2009}, |
| MONTH= |
{December}, |
| VOLUME = |
{09}, |
| ISSUE = |
{I}, |
| PAGES= |
{41--46}, |
| ABSTRACT= |
{The study of the hospital systems is complex because of
the great number of entities which they contain and their
interactions. To manage this complexity, modeling
contributes with the choice of the relevant entities and
thus to the negligence of the nonrelevant entities. The
result of these choices is called model and thus contains
the description of a relevant part of the system. To face
this complexity, it is necessary to use a methodology
which allows the separation of the phases of analysis of
specification, design and implementation (ASCI). In this
paper, we present and we study methodology ASCI and
we try to implement the stages to be followed for the
modeling and the simulation of a service of imagery of a
university military hospital regional of Oran HMRUO
Algérie. For that we build two models: models of
knowledge builds with tool ARIS Toolset and the model
knowledge to implement with SIMULA}, |
| NOTE= |
{modeling, simulation asci methodology,
healthcare system}
}
|
(Status: Accepted)
| @ARTICLE |
{P1170950105, |
| AUTHOR = |
{Boualem Magaz and Toufik Mabed and Ali Abbadi and M’hamed Hamadouche and Adel Belouchrani}, |
| TITLE = |
{Design and Implementation of a Real Time FPGA Based CFAR Processor for
Radar Target Detection Using ML403 FPGA Development Board}, |
| JOURNAL = |
{ICGST International Journal on Programmable Devices, Circuits and Systems, PDCS}, |
| YEAR = |
{2009}, |
| MONTH= |
{December}, |
| VOLUME = |
{09}, |
| ISSUE = |
{I}, |
| PAGES= |
{47--51}, |
| ABSTRACT= |
{The improvement in the development of theoretical
aspect of CFAR radar detection is advanced and very
promising, yet the practical hardware aspect is still
beyond the required high computational signal
processing operations. In this paper, a configurable Field
Programmable Gate Array (FPGA) based hardware
architecture for Ordered Statistics (OS)-CFAR processor
for radar target detection is presented.
The proposed architecture is based on an efficient
procedure for FPGA implementation of the OS-CFAR
detector, based on the (N-K+1)-th maximum
determination. By showing that the determination of the
K-th order out of N reference cells is equivalent to
selecting the (N + 1 - K)-th maximum, the detector that
uses N reference cells can be implemented using only (N-
1) comparators and (N-1) inverters.
The proposed structure, adapted to the ASR-9 radar
parameters, is designed, implemented, and evaluated on
the ML403 FPGA board. The proposed architecture
shows that it can be implemented with the advantages of
a parallel structure and allows an important optimization
of the required FPGA hardware resources utilization. The
system has the advantages of being simple, fast, and
flexible with low development cost. For a reference
window of 16 range cells, the experimental results
carried out using Xilinx development kit showed that the
proposed architecture works properly with a processing
speed of 50MHz (up to 122 MHz using external clock).
The execution time to perform the overall OS-CFAR
detection algorithm is 0.819ms for a data set of 1000
range cells. The FPGA implementation results are
presented and discussed}, |
| NOTE= |
{FPGA, Implementation, OS-CFAR processor,
Radar}
}
|
(Status: Accepted)
| @ARTICLE |
{P1170950106, |
| AUTHOR = |
{Majdi Elhaji and Abdelkrim Zitouni and Rached Tourki}, |
| TITLE = |
{A Low Power ASIC Design of a FSBM Motion Estimator
For H.264AVC}, |
| JOURNAL = |
{ICGST International Journal on Programmable Devices, Circuits and Systems, PDCS}, |
| YEAR = |
{2009}, |
| MONTH= |
{December}, |
| VOLUME = |
{09}, |
| ISSUE = |
{I}, |
| PAGES= |
{53--58}, |
| ABSTRACT= |
{In a video Codec such as H264AVC, motion estimation
comprises one of the most important compression
methods for video communications. Since this task is
computationally intensive to result in large power
consumption, a low-power design is essential for portable
or mobile systems. This paper presents a new Full Search
Block Matching (FSBM) motion estimation architecture
design. Our basic idea is based on shutting down each
processing-element (PE) when it is not under running by
gating its clock with a specific signal. Two versions
(Synchronous and gated clock) of a FSBM motion
estimator have been designed and implemented with a
130 nm CMOS ASIC technology. Experimental results
show that the gated clock version allows a power
consumption witch is 23.86% time lower than the power
dissipated by the synchronous version with only 3.76%
penalty in terms of silicon area. These results show also
that our gated clock architecture is characterized by the
higher speed and the lower dissipated power}, |
| NOTE= |
{Video Codec, Motion Estimation, Dynamic
Power, ASIC Design}
}
|
(Status: Accepted)
| @ARTICLE |
{P1170950107, |
| AUTHOR = |
{S. H. Sfar and I. E. Bennour and R. Tourki}, |
| TITLE = |
{TLM Design Framework of Generic NoC for Performance Exploration}, |
| JOURNAL = |
{ICGST International Journal on Programmable Devices, Circuits and Systems, PDCS}, |
| YEAR = |
{2009}, |
| MONTH= |
{December}, |
| VOLUME = |
{09}, |
| ISSUE = |
{I}, |
| PAGES= |
{59--66}, |
| ABSTRACT= |
{It is estimated that video and audio processing are going
to be common tasks in many applications. These
applications are going to require large storage and
intensive processing of large amount of data. This
evolution of Systems on Chips (SoC) promotes Network
on Chip (NoC) to be “a first class” on chip
communication architecture. NoC reuses many concepts
of computer network, offers high scalability, modularity
and bandwidth. The goal of this paper is to propose a
SystemC transaction level model of generic NoC in 2D
mesh topology. This model aims to provides various QoS
and to have maximum number of parameters for
performance exploration, optimization and above all to
increase its reconfiguration degree. Features of the OSCI
TLM2 have been used to develop such a model}, |
| NOTE= |
{NoC, TLM, OSI stack, quality of service}
}
|
|
